1. Related Applications
This application is related to application Ser. No. 08/570,040 filed on Dec. 11, 1995, now U.S. Pat. No. 5,654,650 assigned to the assignee of the present invention.
2. Field of the Invention
The present invention relates, in general, to programmable logic devices including field programmable gate arrays (FPGAs), and, more particularly, to an apparatus and method for loading data streams used to program FPGAs and for decreasing the amount of time needed to configure FPGAs.
3. Statement of the Problem
Programmable logic devices (PLDs) include programmable logic arrays (PLAs), field programmable gate arrays (FPGAS) and the like. In PLDs, configurable interconnects are used to connect logic elements, which may themselves be programmable, to each other and to input and output ports. To implement a desired circuit, PLDs must be given the information as to what connections are to be made and/or what logic is to be implemented by each of the logic elements. This is accomplished by applying a "configuration data stream" which is an ordered data stream in which each bit is represented by a binary value, to "configuration lines" formed on the PLD.
The configuration data stream is used to program individual switches inside the PLD to a desired state (i.e., on or off). These switches can be implemented from SRAM cells that control pass transistors, antifuse connection points, fuse connection points, or any other equivalent switch implementation. The programmed switches are used to control the configurable routing and logic of the PLD.
A typical PLD may comprise hundreds of programmable switches to accept and hold the configuration data stream. A continuing trend is to increase the logic capabilities of PLDs thereby increasing the number of programmable switches. Some devices employ thousands and tens of thousands of switches per PLD. These switches logically resemble a large addressable memory system with each switch uniquely identified by a column and row address.
In prior PLDs, all of the switches were arranged as a single array. A long shift register containing one bit for each column of switches in the array was used to hold the configuration data for a particular row. A second long shift register was used to load information as to which row in the array the data in the first shift register was to be loaded. Once both shift registers were loaded, all switches in a selected row could be programmed simultaneously by enabling the data in the first shift register to transfer into the programmable switches of the selected row.
Address lines must extend from the first and second shift registers across the entire array of switches in the prior configuration system. Also, each bit of both of the long shift registers must function or it may be impossible to load configuration data into the PLD.
All semiconductor fabrication technology is limited to a certain extent by background defect levels. As semiconductor devices become larger, yields decrease because it becomes more likely that a defect will exist in a particular device. Hence, as PLDs become larger, it is more likely that the long shift registers used in the prior art will be affected by a defect and hence fail to perform up to specifications. Also, it becomes more likely that defects will affect the long address lines required by the prior system. A need exists for a method and apparatus that allows large PLDs to be programmed while achieving reasonable yields in the face of background defect levels.
A fault tolerant system cannot tolerate a large amount of shared elements such as address lines and shift registers used in the prior art.